This invention relates to a BSC macrostructure for three-dimensional wiring and a substrate having the BSC macrostructure and, in particular, to a BSC macrostructure for three-dimensional wiring, which is effective when a boundary scan test is performed, and a substrate having the BSC macrostructure.
A boundary scan test defined by IEEE 1149.1 is widely spread in the electronics industry. The boundary scan test is a testing method in which boundary scan cells (hereinafter referred to as “BSCs”) are arranged around an LSI so as to perform scanning. According to the boundary scan test, it is easy to test a printed board having a plurality of LSIs and to test a multi-chip module (MCM) (for example, see Japanese Unexamined Patent Application Publication (JP-A) No. H9-139409).
In order to perform the boundary scan test, is known a method which uses a BSC buffer included in a special-purpose or a general-purpose switch array or bi-directional driver IC. Referring to FIG. 1, description will be made of the method of performing the boundary scan test by the use of the BSC buffer. In the figure, a substrate 100 is provided with a plurality of I/O pads 101 for external connection and a plurality of pads 102 for mounting bare chips 110 and 120. The bare chip 110 has a plurality of pads 111. Similarly, the bare chip 120 has a plurality of pads 121. The pads 111 and 121 of the bare chips 110 and 120 are connected to the pads 102 of the substrate 100 by wire bonding using bonding wires 140.
When the boundary scan test is performed, a plurality of BSC buffers 103 are arranged on the substrate 100. Under control of a TAP controller 130, the boundary scan test is performed.